1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a polycrystalline silicon electrode interconnection or wiring in contact with an insulating film at a portion thereof having a thinner thickness than at other portions and provided in semiconductor devices such as an MIS (Metal Insulator Semiconductor) LSI, and a DRAM (Dynamic Random Access Memory).
2. Description of the Related Art
The miniaturization of semiconductor elements such as a MIS transistors in an LSI, for example, a memory device such as a DRAM, has led to a gradual thinning of the gate insulating film and capacitor dielectric film of silicon dioxide (SiO.sub.2) therein.
During experiments by the present inventors, it was found that, when the thickness of the gate insulating film of a MIS transistor becomes less then 100 .ANG., for example about 50 .ANG., a remarkable deviation and deterioration of the quality, such as a deviation of the threshold value, and deterioration of the gate breakdown valtage, etc., occurs. Further it was found recognized that, in a DRAM having a stacked type memory cell, when the thickness of a dielectric film forming a memory cell capacitor becomes thin, a short-circuit between the capacitor electrodes is apt to occur.